This section provides information on the libraries needed to simulate your VHDL and Verilog designs.
To make an RTL simulation FPGA-specific, the design must contain instantiated Unified Library or LogiBLOX components. To support these instantiations, Xilinx provides a functional UNISIM library and a behavioral LogiBLOX library. The VHDL and Verilog versions of the UNISIM library differ because of variations in language features and methodologies. You can also use the UNISIM library for post-synthesis, gate-level simulation as discussed in the “VHDL and Verilog Simulation Flow” section.
Use the UNISIM Library for functional simulation only; it contains default unit delays. Structures differ for the library directories for VHDL and Verilog. Only one VHDL library exists for all Xilinx technologies. However, some components contain configuration statements to select the appropriate functionality for a specific architecture. A single library makes it easier to switch between technologies. Because Verilog does not have configuration statements, separate libraries are provided for each technology.
The UNISIM Library contains all the Xilinx Unified Library components inferred by most synthesis tools. In addition, the UNISIM Library contains commonly instantiated components such as IOs and memory components. Use your synthesis tool's module generators or LogiBLOX to generate higher order functions such as adders, counters, and RAM.
Schematic macros are not provided because schematic vendors usually provide the lower-level netlist when a synthesis tool imports a design. This lower-level netlist for a schematic macro is required for implementation as well. You can find VHDL models for DesignWare components in $XILINX/synopsys/libraries/sim/src/xdw.
DesignWare does not currently provide components in Verilog versions.
You can accelerate the VITAL-compliant VHDL version of the UNISIM Library but you cannot back-annotate it with an SDF file. Compile the library for each HDL simulator using the Xilinx-supplied source files in $XILINX/vhdl/src/unisims. Compile the source files into a library named UNISIM.
You do not always have to compile the Verilog version of the UNISIM Library, depending on the Verilog tool. Because there are a few components with functional differences between Xilinx technologies, each supported technology has a separate library, in upper case only. If needed, you can find lower case libraries in the Xilinx Cadence Interface located in $XILINX/verilog/src/technology, where technology is UNI3000, UNI4000E, UNI4000X, or UNI5200.
A few differences exist between the upper and lower case versions of the Verilog UNISIM libraries. For example, because buf, pullup, and pulldown are reserved words in Verilog, the lower case version of the UNISIM library uses buff, pullup1, and pulldown1, and the upper case version uses BUF, PULLUP, and PULDOWN.
You can compile the UNISIM VHDL Library to any physical location on your system. You can find the VHDL source files in $XILINX/vhdl/src/unisims, listed below in the order in which you must compile them with the Synopsys compiler.
You can find the uppercase Verilog components in individual component files in the following directories.
You must refer to the compiled UNISIM Library in your VHDL code to instantiate components from this library in your design for RTL simulation. The VHDL simulation tool must map the logical library to the physical location of the compiled library. Verilog must also map to the UNISIM Verilog library. Even though VHDL component declarations are provided in the library, component declarations are required in the RTL code for synthesis.
Use the SimPrim (simulation primitive) library for post-NGDBuild, post-map partial timing, and full timing back-annotated simulation.
Use the LogiBLOX module generator to create schematic-based modules such as adders, counters and large memory blocks. For your HDL designs, use LogiBLOX to generate large blocks of memory for instantiation. Refer to the “Using LogiBLOX” chapter and LogiBLOX User Guide for more information.
You can compile the LogiBLOX VHDL library to any physical location. You can find the VHDL source files in $XILINX/vhdl/src/logiblox, listed below in the order in which you must compile them.
Simulate LogiBLOX components with behavioral code not intended for synthesis. The synthesizer processes the component as a “black box.” The implementation software reads the NGO file created by LogiBLOX. You can find the source libraries for LogiBLOX in $XILINX/vhdl/src/logiblox. The LogiBLOX tool creates the actual models. You must compile the package files into a library called LOGIBLOX. You should compile the LogiBLOX component model in your working directory with your design.
