Simulation Design Flow Overview

A typical single chip VHDL or Verilog simulation design flow includes the following steps, illustrated in the “HDL Simulation Design Flow” figure.

1. Generation of a VHDL RTL description
   
   
2. VHDL RTL simulation
   
   
3. Synthesis implementation
   
   
4. Optional unit delay gate-level functional simulation
   
   
5. Timing simulation
   
   
   
   

   Figure 5.1 HDL Simulation Design Flow