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Synthesizing/Simulating for VHDL Global Set/Reset Emulation

VHDL requires a testbench to control all signal ports. You can instantiate certain VHDL-specific components, explained in the following sections, in the RTL and post-synthesis VHDL description to allow the simulation of the global signals for global set/reset and global 3-state.

NGD2VHDL creates a port in your back-annotated design entity for stimulating the global set/reset or 3-state enable signals. This port does not actually exist on the configured part.

When running NGD2VHDL, you do not need to use the -gp switch to create an external port if you instantiate a STARTUP block in your implemented design. The port is already identified and connected to the global set/reset or 3-state enable signal. If you do not use the -gp option or a STARTBUF block, you must use special components, as described in the following sections.

Using STARTBUF in VHDL

STARTBUF replaces STARTUP. With STARTBUF you can functionally simulate the GSR/GR net in both function and timing simulation. By connecting the input pin of the STARTBUF to a top-level port and using STARTBUF as the source for all async set/reset signals in a design, Xilinx M1 software can automatically optimize the design to use the GSR/GR. Because you can use STARTBUF in functional simulation (unlike STARTUP), when you use STARTBUF you can map to the GSR/GR in a device. You can still use STARTUP, but it does not always provide correct GSR/GR in HDL flows.

The STARTBUF component passes a reset or 3-state signal in the same way that a buffer allows simulation to proceed and also instantiates the STARTUP block for implementation. One version of STARTBUF works for all devices, however, the XC5200 and the XC4000 STARTUP blocks have different pin names. Implementation with the correct STARTUP block occurs automatically. The following shows an instantiation example of the STARTBUF component.

U1: STARTBUF port map (GSRIN => DEV_GSR_PORT, GTSIN =>DEV_GTS_PORT, CLKIN => `0', GSROUT => GSR_NET, GTSOUT => GTS_NET, Q2OUT => open, Q3OUT => open, Q1Q4OUT => open, DONEINOUT => open):

You can use one or both of the input ports (GSRIN and GTSIN) of the STARTBUF component and the associated output ports (GSROUT and GTSOUT). You can use pins left “open” to pass configuration instructions to the implementation tools by connecting the appropriate signal to the port instead of leaving it open.

Instantiating a STARTUP Block in VHDL

The STARTUP block traditionally instantiates to identify the GR, PRLD, or GSR signals for implementation. However, simulation can occur only when the net attached to the GSR or GTS goes off the chip because the STARTUP block does not have a simulation model. You can use the new components described below to simulate global set/reset or 3-state nets whether or not the signal goes off the chip.

Generating a Reset-On-Configuration in VHDL

The Reset-On-Configuration (ROC) component generates during back-annotation if you do not use the -gp option or STARTUP block options. Therefore, you can instantiate the ROC in the front end to match for functionality with GSR, GR, or PRLD (done in both functional and timing simulation). During back-annotation, the entity and architecture for the ROC component are placed in your design's output VHDL file.

In the front end, the entity and architecture reside in the UNISIM Library, and require a component declaration and instantiation.

The ROC component generates a one-time initial pulse to drive the GR, GSR, or PRLD net starting at time “0” for a user-defined pulse width. You can set the pulse width with a generic in a configuration statement. The default value of “width” is 0 ns, which disables the ROC component and causes a low global set/reset. The netlist itself handles active low resets, requiring you to invert this signal before using it.

The ROC component allows you to simulate with the same testbench as in RTL simulation, and also allows you to control the width of the GSR signal in your implemented design.

One of the easiest methods for mapping the generic involves configuring your testbench. An example testbench configuration for setting the generic follows.

CONFIGURATION cfg_my_timing_testbench OF my_testbench IS
FOR my_testbench_architecture
FOR ALL:my_design USE ENTITY work.my_design(structure);
FOR structure
FOR ALL:roc ENTITY work.roc (roc_v);
GENERIC MAP (width => 100 ms)
END FOR;
END FOR;
END FOR;
END FOR;
END cfg_my_timing_testbench;

The following shows an instantiation example of the ROC component.

U1: ROC port map (O => GSR_NET);

Using ROCBUF in VHDL

The ROCBUF component allows you to provide a stimulus for the ROC signal through a testbench. However, the port connected to it does not implement as a chip pin. Use the -gp switch with NGD2VHDL to use the port in timing simulation. The following example shows an instantiation of the ROCBUF component.

U1: ROCBUF port map (I => SIM_GSR_PORT, O => GSR_NET);

Generating a 3-State-On-Configuration in VHDL

The 3-State-On-Configuration (TOC) component generates if you do not use the -tp option or STARTUP block options. The entity and architecture for the TOC component are placed in your design's output VHDL file.

The TOC component generates a one-time initial pulse to drive the GR, GSR, or PRLD net starting at time `0' for a user-defined pulse width. You can set the pulse width with a generic in a configuration statement. The default value of “width,” 0 ns, disables the TOC component and causes the 3-state enable to be held low. The netlist itself handles active low 3-state enables, requiring you to invert this signal before using it.

The TOC component allows you to simulate with the same testbench as in the RTL simulation, and also allows you to control the width of the 3-state enable signal in your implemented design.

The TOC components require a value for the generic width, usually specified with a configuration statement. Otherwise, you must include a generic map as part of the component instantiation. You can set the generic width with any generic mapping method. Set the “width” generic after consulting The Programmable Logic Data Book for the particular part and mode you have implemented. For example, a XC4000E part can vary from 10 ms to 130 ms. Use the TPOR (Power-On Reset) parameter found in the Configuration Switching Characteristics tables for Master, Slave, and Peripheral modes.

One of the easiest methods for mapping the generic to configure your testbench. An example testbench configuration for setting the generic follows.

CONFIGURATION cfg_my_timing_testbench OF my_testbench IS
FOR my_testbench_architecture
FOR ALL:my_design USE ENTITY work.my_design(structrue);
FOR structure
FOR ALL:toc ENTITY work.toc (toc_v);
GENERIC MAP (width => 100 ms)
END FOR;
END FOR;
END FOR;
END FOR;
END cfg_my_timing_testbench;

The following example shows an instantiation of the TOC component.

U2: TOC port map (O => GTS_NET);

Using TOCBUF in VHDL

The TOCBUF allows you to provide a stimulus for the global 3-state signal (GTS) through a testbench. However, the port connected to it does not implement as a chip pin. Use the -tp switch with NGD2VHDL to use the port in timing simulation. The following example shows an instantiation of the TOCBUF component.

U2: TOCBUF port map (I =>SIM_GTS_PORT, O =>GTS_NET);

Using Oscillators in VHDL

The SimPrim library does not include the Oscillator component because you cannot drive global signals in VHDL designs. After back-annotation, your VHDL design output contains the oscillator entity and architectures. The UNISIM Library instantiates and simulates oscillators for functional simulation. You must set the period of the base frequency for simulation because the default period of 0 ns disables the oscillator. The oscillator's frequency can vary significantly with process and temperature.

Before setting the base period parameter, consult The Programmable Logic Data Book for the part you are using. For example, for a XC4000 on-chip oscillator, the base frequency ranges from 4 MHz to 10 MHz, and is nominally 8 MHz. Therefore, the base period generic “period_8m” for the XC4000E OSC4 VHDL model ranges from 250 ns to 100ns, as shown in the following example.

CONFIGURATION cfg_my_functional_testbench OF my_testbench IS
FOR my_testbench_architecture
FOR ALL: my_design USE ENTITY work.my_design (my_design_rtl);
FOR my_design_rtl
FOR ALL:my_submodule USE ENTITY work.my_submodule (my_submodule_rtl);
FOR my_submodule_rtl
FOR all: osc4 USE ENTITY work.osc4 (structure)
GENERIC MAP (period_8m => 125 nS);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END cfg_my_functional_testbench;

Using Global Set/Reset Emulation in Verilog

For more information, refer to the Cadence User's Manual.

Using Global 3-State Emulation in Verilog

For more information, refer to the Cadence User's Manual.

Using Oscillators in Verilog

For more information, refer to the Cadence User's Manual.

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