Refer to the VHDL and Verilog Simulation Flow figure.
NGDBuild processes multiple device architectures with the same core map and place and route software. NGDBuild performs two functions during design implementation.
The MAP program reads this NGD file and creates a native circuit description (NCD) file, a physical description of your design in terms of the target device.
Next, the PAR program places and routes the NCD file. NGDAnno creates an NGA file, a back-annotated NGD file.