Follow the instructions in the testbench.vhd file included with the Calc tutorial to create a testbench file for your design. See the “FPGA Compiler and Design Compiler Tutorial for XC4000E/L/EX/XL/XLA/XV Designs” chapter for more information. You can use the same testbench for RTL and timing simulation.
After you have created a testbench file, you can begin using the VSS simulator for RTL simulation.
