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Using RTL Simulation

Use RTL simulation to debug your logic before fitting your design into an FPGA.

Generally RTL level simulation does not require VITAL or Verilog unified library models because VHDL simulators can simulate “behavioral code.” However if your design contains instantiated components (such as RAMs, ROMs, input registers, INFF, clock buffers), the simulator must have access to VITAL or Verilog models for these front end unified library components.

During simulation, analyze your design's modules according to hierarchical precedence with the lowest first (analyze the testbench last). Analyze the RTL models for all instantiated primitives, followed by the design files, with the Synopsys VHDLAN command.

vhdlan -i module.vhd
.
.
.
vhdlan -i testbench.vhd

NOTE

Use the -i option on the VHDLAN command. While this option can result in a slight increase in simulation time, it is not dependent on any operating system or C compilers. Additionally, VHDLAN can analyze your design in compiled or interpretive modes. While the compiled mode usually accelerates simulation run times, it reduces debugger visibility into the simulation. For more information, refer to the Synopsys documentation.

After analyzing all your design modules (including the testbench), start the simulator. The simulator comes in two versions, a graphic debugging environment, VHDLDBX, and a command-line driven simulator, VHDLSIM. VHDLDBX allows you to select the desired configuration from a graphic window. VHDLSIM requires you to specify the desired configuration at the command line. In either case, select the configuration name associated with your testbench entity.

For example, consider a testbench with the following entity and architecture statements.

entity my_testbench is
end my_testbench;
architecture my_vectors of my_testbench is
.
.
begin
.
.
end my_vectors;

At a minimum, you then require a configuration of the following type.

configuration my_configuration of my_testbench is
for my_vectors
end for;
end my_configuration;

To start VHDLDBX on this design, perform the following steps.

  1. Enter the following at the UNIX command line.

    vhdldbx

  2. Select my_configuration from the command list.

  3. Press OK.

To start VHDLSIM on this design, enter the following command at the UNIX command line.

vhdlsim my_configuration

For an example of how to use these tools, refer to the “FPGA Compiler and Design Compiler Tutorial for XC4000E/L/EX/XL/XLA/XV Designs” chapter. Also, see the Synopsys user documentation for more information.

The Calc tutorial provides the behv_sim.csh script file. This script illustrates the necessary steps to perform an RTL simulation on the Calc design. You can modify behv_sim.csh to use with your designs. This script analyzes the VHDL files, and starts the VSS VHDL Debugger (VHDLDBX). During simulation, the testbench applies stimulus to the design, and monitors and records its outputs. See the “FPGA Compiler and Design Compiler Tutorial for XC4000E/L/EX/XL/XLA/XV Designs” chapter for more information.

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