Implementing Your Design

After debugging your design using RTL simulation, you can compile it using synthesis and implement it in an FPGA using the Xilinx software. You must implement your design before performing timing simulation.

Use DC Shell commands or Design Analyzer, as described in the “Synthesizing Your Design” chapter, to create the XNF or EDIF netlist file required by the Xilinx software. This gate-level netlist file contains components from the appropriate library but not timing information. The Xilinx software processes the netlist file and places the logical design into the physical architecture of your target FPGA.

After the Xilinx software implements the design, the actual target device timing information is available for timing simulation.

Using the Calc design as an example, the following steps provide an overview of the implementation procedure.

1. Compile the design, targeting the appropriate libraries, and create an XNF or EDIF netlist by executing the following command at the command line.
   
   dc_shell -f calc.script
   
   During processing, the system displays informational messages.
   
   
2. Run NGDBuild to process the netlist. NGDBuild translates the Synopsys-generated netlist to a Xilinx netlist.
   
   ngdbuild -p parttype calc
   
   
3. Run the MAP program. MAP allocates the logic to CLBs and IOBs.
   
   map calc
   
   
4. Run PAR, which produces a placed and routed design. The -w option specifies the output file name.
   
   PAR calc -w calc_routed
   
   
5. Run NGDAnno, which relates the placed and routed design with the original design to ensure the retention of as many of the original component and net names as possible.
   
   ngdanno calc_routed calc
   
   
6. Run NGD2VHDL, which creates a structural VHDL netlist for use as a simulation model and a corresponding SDF file containing timing information.
   
   ngd2vhdl calc_routed
   
   

When simulating, you must analyze your design's modules according to hierarchical precedence with the lowest first (structural netlist first, followed by the testbench).

vhdlan -i routed_design.vhd

vhdlan -i testbench.vhd

NOTE

VHDLAN can analyze your design in compiled or interpretive modes. While the compiled mode usually accelerates simulation run times, it reduces debugger visibility into the simulation. For more information, refer to the Synopsys documentation.

The VHDL Simulator launches and reads in the testbench, the back-annotated VHDL model for your placed and routed design, and the associated SDF file.

For timing simulation, the simulator starts in the same way as for RTL simulation, but with the addition of the following two command line options.

• The name of the SDF file that contains the timing information
  
  
• The instance in the testbench where you apply timing information
  
  

The following examples illustrate these two command line options.

• VHDLSIM Example
  
  vhdlsim -sdf_top my_testbench/instance_name \
  -sdf routed_design.sdf my_configuration
  
  
• VHDLDBX Example
  
  vhdldbx -sdf_top my_testbench/instance_name \
  -sdf routed_design.sdf my_configuration
  
  

Where instance_name is the instance name of the unit under test in your testbench.

NOTE

You can also specify the -sdf_top and -sdf options in the arguments field of the initial window that appears when you start VHDLDBX.

The Calc tutorial provides the tim_sim.csh script file. This script provides the necessary steps to perform a timing simulation with the VSS simulator. You can modify this script to use with your designs. You can use the same testbench you used to perform an RTL simulation to perform a timing simulation.

See the “FPGA Compiler and Design Compiler Tutorial for XC4000E/L/EX/XL/XLA/XV Designs” chapter for more information.