Chapter 3

Synthesizing Your Design

Synthesize and implement your HDL designs for Xilinx FPGA devices with either FPGA Compiler or Design Compiler by using the information in the following sections.

• “Before You Begin” section
  
  
• “Setting the Wire-Load Model” section
  
  
• “Setting the Operating Condition Parameters” section
  
  
• “Configuring IOBs” section
  
  
• “Inserting Clock Buffers” section
  
  
• “Using Memory” section
  
  
• “Performing Boundary Scans” section
  
  
• “Using the Global Set/Reset Net” section
  
  
• “Using the Xilinx DesignWare Library” section
  
  
• “Creating Timing Specifications” section
  
  
• “Compiling Your Design” section
  
  
• “Creating the Area Report” section
  
  
• “Evaluating Timing Delays” section
  
  
• “Generating Reports for Debugging” section
  
  
• “Writing and Saving Your Design” section
  
  
• “Using the Xilinx Development System” section