Verilog Reference Guide

Preface

About This Manual

This manual describes how to use the Xilinx Foundation Express program to translate and optimize a Verilog HDL description into an internal gate-level equivalent.

Before using this manual, you should be familiar with the operations that are common to all Xilinx software tools: how to bring up the system, select a tool to use, specify operations, and manage design data. These topics are covered in the Foundation Series Quick Start Guide.

You must consult The Programmable Logic Data Book for device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging. The Programmable Logic Data Book is available in hard copy and on the Xilinx web site (http://www.xilinx.com). See http://www.xilinx.com/partinfo/databook.htm for the current version of this book.

For specific design issues or problems, use the Answers Search function on the Web (http://www.xilinx.com/support/searchtd.htm) to access the following.

• Answers Database: current listing of solution records for the Xilinx software tools
  
  
• Applications Notes: descriptions of device-specific design techniques and approaches
  
  
• Data Sheets: pages from The Programmable Logic Data Book
  
  
• XCELL Journal: quarterly journals for Xilinx programmable logic users
  
  
• Expert Journals: the latest news, design tips, and patch information on the Xilinx design environment
  
  

If you cannot access the Web, you can install and access the Answers book with the DynaText online browser in the same manner as the Xilinx book collection. The Answers book includes information in the Answers Database at the time of this release.

Manual Contents

This manual covers the following topics.

• Chapter 1, “Foundation Express with Verilog HDL,” discusses general concepts about Verilog and the Foundation Express design process and methodology.
  
  
• Chapter 2, “Description Styles,” presents the concepts you need to make the necessary architectural decisions and use the constructs best suited for synthesis.
  
  
• Chapter 3, “Structural Descriptions,” discusses modules and module instantiations.
  
  
• Chapter 4, “Expressions,” explains how to build and use expressions with constant-valued expressions, operators, operands, and expression bit-widths.
  
  
• Chapter 5, “Functional Descriptions,” describes the construction and use of functional descriptions. Task statements and always blocks are also discussed.
  
  
• Chapter 6, “Register and Three-State Inference,” describes how to report inference results, control inference behavior, and infer cells.
  
  
• Chapter 7, “Foundation Express Compiler Directives,” describes Foundation Express directives and their effect on translation.
  
  
• Chapter 8, “Translating Flip-flops,” explains how to translate hand-instantiated flip-flops to always blocks that can be used with Foundation Express.
  
  
• Chapter 9, “Verilog Syntax,” contains syntax descriptions of the Verilog language as supported by Foundation Express.
  
  

Conventions

Typographical

This manual uses the following conventions. An example illustrates each convention.

• Courier font indicates messages, prompts, and program files that the system displays.
  
  speed grade: -100
  
  
• Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].
  
  rpt_del_net=
  
  Courier bold also indicates commands that you select from a menu.
  
  File Open
  
  
• Italic font denotes the following items.
  
  
  • Variables in a syntax statement for which you must supply values
    
    edif2ngd design_name
    
    
  • References to other manuals
    
    See the Development System Reference Guide for more information.
    
    
  • Emphasis in text
    
    If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
    
    
• Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.
  
  edif2ngd [option_name] design_name
  
  Square brackets also enclose footnotes in tables that are printed out as hardcopy in DynaText^®.
  
  
• Braces “{ }” enclose a list of items from which you must choose one or more.
  
  lowpwr ={on|off}
  
  
• A vertical bar “|” separates items in a list of choices.
  
  lowpwr ={on|off}
  
  
• A vertical ellipsis indicates repetitive material that has been omitted.
  
  IOB #1: Name = QOUT'
  IOB #2: Name = CLKIN'
  .
  .
  .
  
  
• A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.
  
  allow block block_name loc1 loc2 ... locn;
  
  

Online Document

Xilinx has created several conventions for use within the DynaText online documents.

• Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
  
  
• Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.
  
  
• There are several types of icons.
  
  Iconized figures are identified by the figure icon.
  
  
  
  Iconized tables are identified by the table icon.
  
  
  
  The Copyright icon displays in the upper left corner on the first page of every Xilinx online document.
  
  
  
  The DynaText footnote icon displays next to the footnoted text.
  
  
  
  Double-click these icons to display figures, tables, copyright information, or footnotes in a separate window.
  
  
• Inline figures display within the text of a document. You can display these figures in a separate window by clicking the figure.