Outputs

The Mentor interface generates a back-annotated simulation netlist file based on the following:

• QuickPart-based SIMPRIM models and a flat/hierarchical EDIF netlist.
  
  
• VHDL-based SIMPRIM models, a structural VHDL netlist, and a SDF delay file.
  
  
• Verilog-based SIMPRIM models, a structural Verilog netlist, and a SDF delay file.