Functional Simulation

VHDL-on-top designs consist of a VHDL based design referencing EDDM components.

Compiling the Design

Before functionally simulating the mixed VHDL-based design, perform the following steps:

NOTE

This procedure assumes that you are using ModelSim. QuickHDL provides the same functionality as ModelSim. If you are using QuickHDL instead of ModelSim, see the “ModelSim and QuickHDL” appendix for details on how to modify this procedure.

1. Create a working library with vlib.
   
   vlib mywork
   
   
2. Map the library with vmap.
   
   vmap work mywork
   
   
3. If using LogiBLOX modules, use vmap to map to the compiled LogiBLOX modules location.
   
   vmap logiblox $XILINX/mentor/data/vhdl/logiblox
   
   
4. Compile the VHDL source files with vcom.
   
   vcom [options] design_name
   
   See the Mentor documentation for a description of the available options.
   
   

Simulating the Design

To simulate VHDL-at-top designs, invoke QuickHDL Pro, which in turn invokes QuickSim to simulate the Unified Libraries elements and ModelSim to simulate the VHDL-based blocks as needed.

1. Double-click the left mouse button on the QuickHDL Pro icon in the Design Manager Tools window.
   
   Alternatively, you can select the top-level component in the Navigator window and click the right mouse button to invoke QuickHDL Pro.
   
   The QHDL Pro dialog box appears, as shown in the “QHDL Pro Dialog Box” figure.
   
   
2. In the Invoke On field, click on Configuration.
   
   
3. In the Name field, type the path name of the configuration from Gen_Arch.
   
   
4. Click on Qhpro.
   
   
5. Click on OK to proceed with simulation.
   
   

For details on using QHDL Pro, refer to the Mentor Graphics Documentation.

Figure 5.6 QHDL Pro Dialog Box

Optional Post-Synthesis Functional Simulation

You can optionally re-simulate the design after synthesis to an EDIF or XNF file to ensure that the design's functionality remains optimal. To do so, follow these steps:

1. Create the NGO from EDIF2SIM and XNF2SIM for later use in the implementation tool. EDIF2SIM and XNF2SIM NGO files must be placed in your top level directory or you must modify the macro search path in the Xilinx Design Manager to include the location of NGO files. EDIF2SIM or XNF2SIM do not have the macro search path functionality. You must have the EDIF2SIM and XNF2SIM NGO files in the same directory as your top-level EDIF or XNF.
   
   
2. If the synthesis tool created an EDIF file, submit the file to pld_edif2sim, then submit it to ModelSim.
   
   
3. If the synthesis tool created an XNF file, submit the file to pld_xnf2sim, then submit it to ModelSim.