Design Implementation

Once you complete the functional simulation and synthesis steps for a VHDL-on-top design, you are ready to implement your design in an FPGA or CPLD. You perform implementation with the Xilinx Design Manager, a graphical design flow and project manager. In the Mentor interface, the Xilinx Design Manager is called pld_dsgnmgr. You invoke pld_dsgnmgr from the Mentor Design Manager or from a UNIX shell.

Design entry of VHDL-on-top designs produces NGO files for schematic modules and XNF or EDIF files for the synthesized portion of the design. The following figure shows the design flow for implementing such a mixed design.

Figure 5.7 Design Implementation

The Xilinx Design Manager takes in your design, represented by the EDIF or XNF file from synthesis and the NGO file for the schematic module from pld_edif2sim. It first translates the design into a flattened or hierarchical netlist, then optimizes, places, and routes the design. You can also use the Xilinx Design Manager to generate SDF timing information that you can import into ModelSim. For a more in-depth discussion of the flow, including advanced implementation options, see the Development System User Guide.

By default, the Xilinx Design Manager looks for the NGO files for the schematic modules in the directory where it was invoked. You have the option of putting all of the NGO files in another directory. To direct the Xilinx Design Manager to look for the NGO files in another directory, follow these steps:

1. In the Xilinx Design Manager window, select Utilities Template Manager.
   
   
2. Select the Family for implementation.
   
   
3. Select Implementation Templates.
   
   
4. Select the Template you wish to modify.
   
   If you have not created your own template, you may modify the default one.
   
   
5. Select Edit.
   
   
6. Select Interface.
   
   
7. Fill in the Macro Search Path box with the path to the NGO files.
   
   
8. Under simulation Data Options, select the VHDL Format as shown in the following figure.
   
   

   Figure 5.8 Implementation Options Dialog Box

To implement your design follow these steps:

1. Within the Mentor Design Manager, select the EDIF icon for your design in the Navigator, then select Right Mouse Button Open pld_dsgnmgr. The Xilinx Design Manager appears as shown in the “Xilinx Design Manager” figure. The tool automatically creates a Xilinx project called your_design_name. Xilinx project information is kept in a file called xproj/your_design_name.prj by default.
   
   

   Figure 5.9 Xilinx Design Manager

   Each project is associated with objects known as versions and revisions. Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop); revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options).
   
   
2. Within the Xilinx Design Manager, select Design Implement.
   
   The Implement dialog box opens as shown in the following figure and displays fields for part type, design version, and revision.
   
   

   Figure 5.10 Implementation Dialog Box

3. The Xilinx Design Manager reads the part type from the design.
   
   If you wish to specify the part type manually, click the Select button to display a pull-down listing of available devices. Choose a family, a device, a package, and a speed grade. Click OK. The part number is inserted into the Part field in the Implement dialog box.
   
   
4. Click on Options. The Options dialog box appears as shown in the “Options Dialog Box” figure.
   
   

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   NOTE

   The CPLD Options dialog box does not have a Configuration Template section, nor does it have a Produce Logic Level Timing Report checkbox.

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   Figure 5.11 Options Dialog Box

5. Click the Browse button next to the User Constraints field. Select the appropriate .ucf file from the design directory, then Click OK.
   
   
6. You may use your own template for implementation or configuration. For instance, you might have an implementation where the macro search path template has been set. If so, select the proper template under Program Option Templates.
   
   
7. Under Optional Targets, make sure the following are selected:
   
   
   • Produce Timing Simulation Data: This generates a back-annotated VHDL file that you can import into the Mentor Graphics tools.
     
     
   • Produce Configuration Data: This generates a programming bitstream suitable for downloading into the Xilinx device.
     
     
   • Produce Post Layout Timing Report: This generates a timing report file based on how the design is actually routed.
     
     You can also select the following option (FPGAs only):
     
     
   • Produce Logic Level Timing Report: This generates a preliminary (pre-place and route) timing report based on the number of logic levels in each signal path. Since it is generated before the place-and-route layout step, it does not contain information on device routing. Looking at this report before place and route can be useful for seeing how much routing slack you have in a design.
     
     
8. Select the Edit Template button on the right hand side of the Implementation field. The Implementation Options dialog box appears as shown in the following figure.
   
   

   Figure 5.12 Changing Simulation Data Option

9. Select the Interface tab. In the Interface pane, look under Simulation Data Options and verify that Format is set to VHDL and that Correlate Simulation Data to Input Design is selected. In the Vendor field, select generic.
   
   
10. Click OK to return to the Options window.
    
    
11. Click OK to return to the Implementation dialog box.
    
    
12. In the Xilinx Design Manager window, verify that you have selected the current version and revision you wish to work on, then click Run. The Flow Engine comes up as shown in the following figure.
    
    

    Figure 5.13 The Xilinx Flow Engine

    The status bar shows the progress of the implementation flow with the following stages:
    
    
    • Translate: Converts the design EDIF or XNF file into an NGD (Native Generic Design) file.
      
      
    • Map: Groups basic elements (bels) such as flip-flops and gates into logic blocks (comps). Also generates a logic-level timing report if desired.
      
      
    • Place&Route: Places comps into the device, and routes signals between them.
      
      
    • Timing: Generates timing simulation data and an optional post-layout timing report.
      
      
    • Configure: generates a bitstream suitable for downloading into and configuring a device
      
      When the implementation completes, an Implementation Status box appears with:
      
      Implementing revision ver1->rev1 completed successfully.
      
      
13. Click on View Logfile to display the logfile from Flow Engine in the vi text editor.
    
    
14. To exit the viewer, type :q! and press Return.
    
    
15. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.
    
    

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    NOTE

    To use another text editor, such as Emacs, as the report viewer, select File Preferences from the Xilinx Design Manager.

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For VHDL-based designs, the Xilinx Design Manager produces a VHDL file and a SDF file that expresses timing and simulation in SIMPRIM library elements instead of Unified Libraries elements.