Design Entry

Enter your pure VHDL design as described in the “HDL Design Entry” section of the “HDL Designs” chapter.

If you wish to insert a schematic module into your VHDL code, Mentor QuickHDL Pro allows you to co-simulate your VHDL portion in ModelSim with your schematic portion in QuickSim II.

Your synthesizer requires you to treat the schematic module as a black box. You must use pld_men2edif and pld_edif2sim to create a NGO file for the schematic component so the Xilinx implementation tools can merge it in the module during implementation.

Figure 5.2 Design Entry for a Mixed Schematic and VHDL Design with VHDL on Top

To enter a mixed schematic and HDL design with VHDL on top, perform the following procedure. The “Design Entry for a Mixed Schematic and VHDL Design with VHDL on Top” figure shows the flow diagram for this procedure.

1. Open pld_dmgr.
   
   
2. Open pld_da and generate EDDM for the schematic module.
   
   
3. Create the NGO file for implementation. To accomplish this, you use pld_men2edif to convert the EDDM for schematic module to EDIF and then use pld_edif2sim to create the NGO file. The procedure for doing this is as follows:
   
   
   1. Open pld_men2edif.
      
      A dialog box opens as shown in the following figure.
      
      

      Figure 5.3 Mentor to EDIF Netlister Dialog Box

   2. Fill in the component name of the existing schematic based module. The module must have a symbol for its top-level netlist. There can be no chip-level I/Os.
      
      
   3. Select a viewpoint that properly sets the schematic parameters such that the EDIF is properly generated.
      
      
   4. Select the Bus Dimension Separator Style that matches your synthesizer. This is important; if your synthesizer uses one bus style and the EDIF/NGO from your schematic uses another style, the implementation tool does not merge the schematic module with the rest of the design, thus leaving it unexpanded.
      
      
   5. Choose the technology.
      
      
   6. Click OK.
      
      
   7. Create the NGO from EDIF2SIM and XNF2SIM for later use in the implementation tool. EDIF2SIM and XNF2SIM NGO files must be placed in your top level directory or you must modify the macro search path in the Xilinx Design Manager to include the location of the NGO files. EDIF2SIM or XNF2SIM do not have the macro search path functionality. You must have the EDIF2SIM and XNF2SIM NGO files in the same directory as your top-level EDIF or XNF.
      
      
   8. Open pld_edif2sim.
      
      The dialog box opens as shown in the following figure.
      
      

      Figure 5.4 Pld_edif2sim Dialog Box

   9. Specify the source of the EDIF file as either a Mentor, Synopsys, or Xilinx compatible EDIF. This step selects the appropriate implementation libraries.
      
      
   10. Enter the name for the EDIF file created above in step b that will be used for the NGO file.
       
       
   11. Enter the name of the NGO file based on the component name used in the VHDL instantiation.
       
       
   12. Select a Xilinx technology.
       
       
   13. Select the NGO (only) output.
       
       
   14. In the “Enter additional directories to search” field, enter all the directory pathnames that the program should search to find supporting EDIF, XNF, and NGO files.
       
       
   15. Click OK to produce the NGO macro file of the schematic component.
       
       
4. Use pld_dve to set the simulation viewpoint.
   
   
5. Open GEN_ARCH to generate the VHDL for module.
   
   The dialog box opens as shown in the following figure.
   
   

   Figure 5.5 Create a VHDL Architecture from an EDDM Component Dialog Box

6. Enter the EDDM component name for the schematic.
   
   
7. Indicate the directory where the VHDL source files from GEN_ARCH are to be placed.
   
   
8. Specify the appropriate ModelSim initialization file. See the Mentor Graphics Documentation for details.
   
   
9. Enter the library name in which the compiled code will be placed. You can place it in the work library.
   
   
10. Leave the other boxes blank and click OK to produce the required output.
    
    
11. Use a Text Editor to create RTL VHDL to be synthesized for the rest of the design. Include the component declaration and instantiation for the schematic module.
    
    
12. Perform synthesis to generate EDIF or XNF for the whole design with a black box for the schematic module.