Functional Simulation

Mixed-model schematic-based designs can be composed of schematic elements from the Unified Libraries, VHDL, XNF-based components, or EDIF-based components. The VHDL-based components will later have FILE=edif_path properties for implementation.

You can simulate the design either before or after you synthesize the HDL module.

Functional Simulation Before Synthesis

The flow diagram for this procedure is shown in the “Performing Functional Simulation Before Synthesis on Mixed-Model Schematic-on -Top Designs” figure. Follow these steps to simulate your design before you synthesize it:

1. Generate a symbol for the HDL module with pld_da.
   
   
2. Instantiate the symbol on the schematic.
   
   
3. Put FILE=xnf_file_pathname or FILE=edif_file_pathname property on the symbol of the synthesized module.
   
   
4. Create a viewpoint for the top-level design using pld_dve:
   
   pld_dve -s design_name technology [viewpoint_name]
   
   
5. Run QuickHDL Pro to simulate the design by typing the following syntax:
   
   qhpro [options] design_name
   
   Alternate ways to invoke QuickHDL Pro are to double-click the left mouse button on the QuickHDL Pro icon in the Design Manager Tools window or to select the top-level component in the Navigator window and click the right mouse button.
   
   The QHDL Pro dialog box appears, as shown in the following figure.
   
   

   Figure 6.3 QHDL Pro Dialog Box

6. In this dialog box, click on EDDM Design in the Invoke On field.
   
   
7. In the Pathname field, type in the path name of the component.
   
   
8. Type the symbol name in the Symbol field only. This step is optional.
   
   
9. Type the interface name in the Interface field only. This step is optional.
   
   
10. Click OK to invoke the ModelSim simulator and perform simulation.
    
    
11. After simulation, synthesize the HDL module with Synopsys' Design Compiler, Synopsys' FPGA Compiler, Exemplar Logic's Galileo, or another synthesizer that creates an EDIF or XNF file for Xilinx.
    
    

    Figure 6.4 Performing Functional Simulation Before Synthesis on Mixed-Model Schematic-on -Top Designs

Functional Simulation After Synthesis

You can optionally re-simulate the design at this point to ensure that the design's functionality remains optimal. This method for simulating your design does not require the use of QuickHDL pro. The flow diagram for this procedure is shown in the “Performing Functional Simulation After Synthesis on Mixed-Model Schematic-on -Top Designs” figure.

If the synthesis tool created an EDIF file, you can include a symbol for the module within the top level design with file=edif_file_name. Then submit the whole design to pld_edif2sim, and then submit it to pld_quicksim.

If the synthesis tool created an XNF file, you can include a symbol for the module within the top level design with file=xnf_file_name. Then submit the whole design to pld_edif2sim, and then submit it to pld_quicksim.

Follow these steps to simulate by this method:

1. Synthesize the HDL module that is being included on the schematic, and create an EDIF or XNF file from that synthesis.
   
   
2. Create a symbol for the HDL module with pld_da and add the file=edif_file_name or file=xnf_file_name property to the symbol. Instantiate the symbol on the top level design.
   
   
3. Run pld_men2edif on the top level design to create an EDIF for the whole design. Make sure to specify the appropriate bus delimiter to match the synthesized module.
   
   
4. Run pld_edif2sim to convert it to a Mentor EDDM single object:
   
   pld_edif2sim edif_file symbol_component_name technology
   {-m|-s} -eddm
   
   Use -m if the synthesis was performed with a Mentor tool; use -s if the synthesis was performed with a Synopsys tool.
   
   
5. Perform functional simulation with pld_quicksim:
   
   pld_quicksim design_name[/viewpoint_name]
   
   

   Figure 6.5 Performing Functional Simulation After Synthesis on Mixed-Model Schematic-on -Top Designs