Design Entry

Design entry consists of two parts, VHDL module design entry and schematic entry.

VHDL Module Design Entry

To enter the VHDL module of your design and to get it ready for functional simulation and implementation, perform the following steps:

1. Enter the VHDL portion of your design as described in the “HDL Design Entry” section of the “HDL Designs” chapter.
   
   
2. When you have the RTL description for the module(s), create a working directory for the VHDL description.
   
   vlib mywork
   
   

   ---

   NOTE

   If you map to a work library other than the default work library, map the library with vmap as follows:

   ---

   vmap work mywork
   
   
3. Compile the VHDL source files with vcom.
   
   vcom [options] design_file(s) -qhpro_syminfo
   
   
4. In pld_da, use File Generate Symbol to import VHDL and create a symbol for the VHDL module as shown in the following figure.
   
   

   Figure 6.2 Generate Symbol Dialog Box

5. On the symbol, add the file=xnf_file_pathname or file=edif_file_pathname property with a value that specifies the path to the XNF or EDIF file that will be synthesized from the RTL description you created above.
   
   
6. Check and save the new symbol.
   
   

Refer to the Mentor documentation for details on using Generate Symbol.

Schematic Entry

1. Enter the top-level and lower-level schematic portions as described in the “Design Entry” section of the “Schematic Designs” chapter.
   
   
2. Instantiate the symbol created for the VHDL module on the top-level design.