Design Implementation

After functional simulation, use a synthesis tool that creates a Xilinx compatible EDIF or XNF file to synthesize certain blocks of the design described in VHDL.

After synthesis, you must attach a FILE=design.edif or FILE=design.xnf property to the VHDL-based block symbol in the schematic before you submit the top-level EDDM design to pld_men2edif.

Converting the EDDM Design

You convert the top-level EDDM design to EDIF with the pld_men2edif utility. To convert your design to EDIF, follow these steps.

1. In the Mentor Design Manager, double-click the left mouse button on the pld_men2edif icon.
   
   The dialog box shown in the following figure appears.
   
   

   Figure 6.6 Mentor to EDIF Netlist Dialog Box

2. In the Component Name field, enter the component name, or click on Navigator to browse a list of design names.
   
   
3. In the From Viewpoint field, you can enter the viewpoint name if you do not want to use the default viewpoint. Alternatively, in step 2 you can select a viewpoint under the component.
   
   
4. Select the appropriate architecture for your design in the PLD Technology field.
   
   
5. Select the desired bus notation style.
   
   Be careful to select the Bus Dimension Separator Style that matches your synthesizer's style. Otherwise busses between the schematic portion and the HDL portion will not match up in the implemented design.
   
   
6. Click on OK.
   
   pld_men2edif now produces an EDIF file that you can submit to the Xilinx Design Manager, pld_dsgnmgr. The output name is component_name.edif.
   
   

Implementing the Design

The Xilinx Design Manager, pld_dsgnmgr, can accept an EDIF file, or if your design is a pure XNF design, it can accept an XNF file.

In the Mentor Design Manager, double-click the left mouse button on the pld_dsgnmgr icon.

Since the implementation is essentially the same as for a pure schematic design, follow the directions in the “Implementing Schematic Designs” section of the “Schematic Designs” chapter.

Normally you need an EDIF file to bring back into the EDDM environment. But you have the option of creating a VHDL or Verilog and an SDF file instead of an EDIF file, which you can submit to ModelSim for timing simulation.